Category
Hardware & Systems
Job Type
Full-time
Experience
Mid-Level
Job Description
Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures.
Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred.
Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.
Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
We have multiple openings.
DROP US YOUR LINKEDIN PROFILE OR CV
Other Openings
Posted September 9, 2026
Posted September 9, 2026
Company Info
U
Ubitium
Builds a universal RISC-V processor that replaces separate CPU, DSP, GPU and FPGA chips with a singl...
Industries
AI & Defence SoftwareSensors & EW
Founded2024
Company Size11-50
HeadquartersDusseldorf, Germany
WebsiteVisit Website →
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