Category
Software & Data
Job Type
Full-time
Experience
Mid-Level
Job Description
December 25, 2025
Focus areas include but are not limited to: RTL synthesis, STA, timing closure, constraints, sign-off.
Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools; processor/SoC experience preferred.
Master's degree (or equivalent) and 2+ years of hands-on experience in a relevant role.
Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
DROP US YOUR LINKEDIN PROFILE OR CV
Other Openings
Posted April 2, 2026
Posted April 2, 2026
Company Info
U
Ubitium
Builds a universal RISC-V processor that replaces separate CPU, DSP, GPU and FPGA chips with a singl...
Industries
AI & Defence SoftwareSensors & EW
Founded2024
Company Size11-50
HeadquartersDusseldorf, Germany
WebsiteVisit Website →
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